1. Field of the Invention
The present invention relates to computer-aided design tools for electrical circuits, and more particularly to a methodology for synthesizing a circuit from a hardware description language specification into a gate-level implementation of the circuit.
2. Related Art
Circuit design is presently accomplished primarily through the use of computer aided design (CAD) tools, which take as input a circuit specification and automatically generate circuit descriptions suitable for implementation. Circuits are initially specified in a hardware description language, such as VHDL or Verilog. The VHDL standard is codified in Institute for Electrical and Electronic Engineers (IEEE) standard 1076-1993. The Verilog standard is codified in IEEE standard 1364-1995.
A hardware description language (HDL) specification of a circuit typically includes a set of equations that specify how the circuit behaves functionally. These equations are xe2x80x9csynthesizedxe2x80x9d into a gate-level implementation of the circuit, which specifies the logic gates that are used to implement the circuit as well as the interconnections between the logic gates. After the circuit is synthesized into an implementation, the system typically performs placement and routing operations on the implementation to produce a final layout for the circuit.
As new semiconductor processing technologies make it possible to integrate larger numbers of devices on a semiconductor chip, circuit designs are growing increasing more complex, involving progressively larger numbers of gates. Unfortunately, the synthesis process can take a great deal of time for larger circuits, because many of the operations performed by the synthesis tool require super-linear, and even exponential execution time. To remedy this problem, a circuit designer typically breaks up a large circuit into smaller modules, which are coupled together by inter-module signal lines. The circuit designer then defines a set of timing constraints on the inter-module signal lines to xe2x80x9cbudgetxe2x80x9d propagation delay between the modules. Next, modules are separately compiled to arrive at a gate-level implementation. Finally, the timing for the circuit is analyzed to determine whether the circuit meets its timing requirements. If not, the timing constraints are adjusted to re-budget the propagation delay, and the process is repeated until the timing requirements are ultimately met.
The process of defining and adjusting timing constraints is referred to as xe2x80x9ctime budgeting.xe2x80x9d The more accurate the time budgeting process is, the faster the synthesis process will converge to an implementation that meets timing requirements. Time budgeting is typically accomplished by looking at the number of logic levels (or gates) that a signal path traverses within a module, and adjusting the constraints based upon the number of logic levels. However, as semiconductor technologies move deeper into sub-micron geometries, the number of logic levels becomes increasingly less important. Instead, the amount of wire, or wire load becomes the dominant factor in determining the timing of a design.
Hence, what is needed is a computer aided design tool that performs time budgeting based for the synthesis process based upon wire load, not the number of logic levels.
One embodiment of the present invention provides a system for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information. The system receives a circuit divided into modules coupled together by a number of signal lines. The system defines a first set of timing constraints, and uses the first set of timing constraints to compile the circuit from a hardware description language specification into a first gate-level implementation. Next, the system performs a timing analysis on the first gate-level implementation to determine positive or negative slack values for the signal lines. These slack values specify amounts of extra propagation delay available on the signal lines. Next, the slack values are used to define a second set of timing constraints by allocating the slack values between the modules based upon wireload information. This wireload information may include such parameters as gate delays and drive strengths for gates coupled to the signal lines. The second set of timing constraints is used to compile the circuit into a second gate-level implementation. If necessary, the process of compilation, timing analysis and allocation of slack values may be repeated until the circuit meets all timing constraints.